部件型号 |
厂商 |
描述 |
|
actel |
CQFB To FBGA Adapter Sockets Designed For Space, Metal To Metal, Antifuse Field Programmable Gate Array |
|
actel |
CQFB To FBGA Adapter Sockets Designed For Space, Metal To Metal, Antifuse Field Programmable Gate Array |
|
actel |
ETHERNET MEDIA ACCESS CONTROLLER |
|
actel |
Bus Controller, DMA Backend Interface To External Memory |
|
xilinx |
The Xilinx® CAN IP core is ideally suited for automotive and industrial applications such as automotive gatewaysand body control unitsand automotive test equipm |
|
xilinx |
Reed-Solomon Encoder and Decoder are commonly used in data transmission and storage applicationsand such as broadcast equipmentand wireless LANsand cable modems |
|
xilinx |
The VLYNQ core is comprised of logic dedicated to transmitting transactions onto the serial Tx lines and logic dedicated to receiving transactions from the seri |
|
xilinx |
The Interleaver/De-interleaver LogiCORE module is a high-speedand compact design that is fully synchronousand using a single clock. It's parameterizable feature |
|
xilinx |
REED SOLOMON ENCODER IMPLEMENTS MANY DIFFERENT REED SOLOMON CODING STANDARDSThe Reed-Solomon Encoder LogiCORE module is a high speedand compact design that impl |
|
xilinx |
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception. Compatible with many common standards. |
|
xilinx |
32-BIT INITIATOR/TARGET V3 AND V4 FOR PCI |
|
xilinx |
V3 AND V4 64-BIT VIRTEX AND SPARTAN AND VIRTEX PRODUCT LOUNGE FOR PCI CORES |
|
xilinx |
LogiCORE POS-PHY L3 Link Layer Interface, Multi - Channel |
|
xilinx |
LogiCORE Viterbi Decoder |
|
microsemi |
CQFB To FBGA Adapter Sockets Designed For Space, Metal To Metal, Antifuse Field Programmable Gate Array |
|
microsemi |
CQFB To FBGA Adapter Sockets Designed For Space, Metal To Metal, Antifuse Field Programmable Gate Array |
|
microsemi |
COREU1LL-UTOPIA LEVEL 1 LINK-LAYER INTERFACE |
|
microsemi |
Bus Controller, DMA Backend Interface To External Memory |
|
microsemi |
Core1553BRT Mil-STD-1553B Remote Terminal |
|
microsemi |
CORE8051 USED IN EMBEDDED SYSTEM CONTROL |
|
microsemi |
CQFB To FBGA Adapter Sockets Designed For Space, Metal To Metal, Antifuse Field Programmable Gate Array |
|
microsemi |
CORE16X50 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER |
|
microsemi |
CORECORDIC CORDIC RTL GENERATOR USED IN COORDINATE ROTATION DIGITAL COMPUTER (CORDIC) ROTATOR FUNCTION FOR ACTEL FPGAS |
|
microsemi |
COREU1PHY-UTOPIA LEVEL 1 PHY INTERFACE |
|
microsemi |
COREU1LL-UTOPIA LEVEL 1 LINK-LAYER INTERFACE |
|
microsemi |
CQFB To FBGA Adapter Sockets Designed For Space, Metal To Metal, Antifuse Field Programmable Gate Array |
|
microsemi |
CORE8051 USED IN EMBEDDED SYSTEM CONTROL |
|
xilinx |
The PCI-X Interface is a pre implemented and fully tested module for Xilinx FPGAs. This significantly reduces engineering time required to implement the PCI-X portion of your design. |
|
xilinx |
The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
|
xilinx |
The Initiator/Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
|
xilinx |
The USB 2.0 protocol multiplexes many devices over a singleand half-duplex serial bus. The bus runs at 480 Mbps or at 12 Mbps and is designed to be plug-and-play. |
|
xilinx |
The 3GPP LTE Channel Decoder provides a high-performanceand optimized decode function for the Uplink Shared Channel (UL-SCH)and as defined in 3GPP TS 26.212 v9.3.0. |
|
xilinx |
Logicore IP Is A High-Performance, Low Cost Flexible Solution |
|
xilinx |
The IEEE 802.16e CTC Decoder Core performs iterative decoding of channel data that has been encoded as described in Section 8.4.9 of the IEEE Std 802.16e specification. |
|
xilinx |
HIGH PERFORMANCE IP CORE IMPLEMENTS AN OBSAI RP3 INTERFACE |
|
xilinx |
The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
|
xilinx |
Logicore IP Serial Rapidio Endpoint |
|
xilinx |
The TCC decoder is used in conjunction with a TCC encoder to provide a reliableand extremely effective way to transmit data over noisy data channels. |
|
xilinx |
The EMAC Interface design is a soft intellectual property (IP) core designed for implementation in several Xilinx FPGAs. |
|
microsemi |
ARINC 429 BUS INTERFACE USE AS ARINC 429 TRANSMITTER (TX) OR RECEIVER (RX) |
|
xilinx |
The Image Statistics LogiCORE IP implements the computationally-intensive metering functionality common in digital camerasand camcorders and imaging devices. |
|
xilinx |
The PCI-X Interface is a pre implemented and fully tested module for Xilinx FPGAs. This significantly reduces engineering time required to implement the PCI-X portion of your design. |
|
xilinx |
The Motion Adaptive LogiCORE IP allows the motion detection function to be used independently of the noise reduction function for applications where noise reduction is not needed. |
|
microsemi |
Core1553BRT Mil-STD-1553B Remote Terminal |
|
xilinx |
LOGICORE IP, DISPLAYPORT INTERCONNECT PROTOCOL |
|
xilinx |
LOGICORE IP 3GPP LTE MIMO DECODER V1.0 |
|
xilinx |
LOGICORE IP PEAK CANCELLATION CREST FACTOR REDUCTION |
|
microsemi |
Bus Controller, DMA Backend Interface To External Memory |
|
microsemi |
Core1553BRT Mil-STD-1553B Remote Terminal |
|
microsemi |
ARINC 429 BUS INTERFACE USE AS ARINC 429 TRANSMITTER (TX) OR RECEIVER (RX) |