EF-DI-PCI-AL-SITE |
xilinx |
The PCI-X Interface is a pre implemented and fully tested module for Xilinx FPGAs. This significantly reduces engineering time required to implement the PCI-X portion of your design. |
EF-DI-PCI32-IP-SITE |
xilinx |
The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
EF-DI-PCI32-SP-PROJ |
xilinx |
The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
EF-DI-PCI64-IP-SITE |
xilinx |
The Initiator/Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
EF-DI-PCIE-PIPE-SITE |
xilinx |
The Xilinx Spartan-3 LogiCORE Endpoint PIPE for PCI Express® (PCIe®) protocol layer core is available for Xilinx low-cost 90nm Spartan-3/3E/3A families. PCIe is a high-speed duplex serial interface standard supported by many industry leaders. |
EF-DI-PCIX-V5-SITE |
xilinx |
The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
EF-DI-PCIX64-VE-SITE |
xilinx |
The PCI-X Interface is a pre implemented and fully tested module for Xilinx FPGAs. This significantly reduces engineering time required to implement the PCI-X portion of your design. |
EF-DI- DISPLAYPORT-AUDIO-SITE |
Xilinx Inc |
DISPLAYPORT WITH SECONDARY AUDIO |
EF-DI- DISPLAYPORT-AUDIO-WW |
Xilinx Inc |
DISPLAYPORT WITH SECONDARY AUDIO |
EF-DI-10-100-EMAC-SITE |
xilinx |
The EMAC Interface design is a soft intellectual property (IP) core designed for implementation in several Xilinx FPGAs. |
EF-DI-10GBASE-KR-PROJ |
Xilinx Inc |
10 GB ETHERNET PCS/PMA WITH FEC |
EF-DI-10GEMAC-PROJ |
xilinx |
LOGICORE, 10 GIGABIT ETHERNET MAC, PROJECT LICENSE |
EF-DI-10GEMAC-SITE |
xilinx |
Xilinx provides a parameterizable LogiCORE IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. |
EF-DI-CAN-XA-SITE |
xilinx |
The Xilinx® CAN IP core is ideally suited for automotive and industrial applications such as automotive gatewaysand body control unitsand automotive test equipmentand instrument clustersand sensor controlsand and industrial networks. |
EF-DI-CAN-XC-SITE |
xilinx |
The Xilinx® CAN IP core is ideally suited for automotive and industrial applications such as automotive gatewaysand body control unitsand automotive test equipm |
EF-DI-CCM-SITE |
xilinx |
LOGICORE, COLOR CORRECTION MATRIX, SITE LICENSE |
EF-DI-CFA-SITE |
xilinx |
LOGICORE, COLOR FILTER ARRAY INTERPOLATI |
EF-DI-CHDEC-LTE-SITE |
xilinx |
The 3GPP LTE Channel Decoder provides a high-performanceand optimized decode function for the Uplink Shared Channel (UL-SCH)and as defined in 3GPP TS 26.212 v9.3.0. |
EF-DI-CHENC-LTE-SITE |
xilinx |
The 3GPP LTE Channel Encoder performs the 'outer' transmit functions for the Physical Downlink Shared (PDSCH)and Multicast (PMCH)and Paging (PPCH)and Control (PDCCH) and Broadcast (PBCH) channels. |
EF-DI-CHEST-LTE-SITE |
xilinx |
LOGICORE, 3GPP LTE CHANNEL ESTIMATOR, SITE LICENSE |