| EF-DI-10-100-EMAC-SITE |
xilinx |
The EMAC Interface design is a soft intellectual property (IP) core designed for implementation in several Xilinx FPGAs. |
| EF-DI-10GEMAC-PROJ |
xilinx |
LOGICORE, 10 GIGABIT ETHERNET MAC, PROJECT LICENSE |
| EF-DI-10GEMAC-SITE |
xilinx |
Xilinx provides a parameterizable LogiCORE IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. |
| EF-DI-CAN-XA-SITE |
xilinx |
The Xilinx® CAN IP core is ideally suited for automotive and industrial applications such as automotive gatewaysand body control unitsand automotive test equipmentand instrument clustersand sensor controlsand and industrial networks. |
| EF-DI-CAN-XC-SITE |
xilinx |
The Xilinx® CAN IP core is ideally suited for automotive and industrial applications such as automotive gatewaysand body control unitsand automotive test equipm |
| EF-DI-CCM-SITE |
xilinx |
LOGICORE, COLOR CORRECTION MATRIX, SITE LICENSE |
| EF-DI-CFA-SITE |
xilinx |
LOGICORE, COLOR FILTER ARRAY INTERPOLATI |
| EF-DI-CHDEC-LTE-SITE |
xilinx |
The 3GPP LTE Channel Decoder provides a high-performanceand optimized decode function for the Uplink Shared Channel (UL-SCH)and as defined in 3GPP TS 26.212 v9.3.0. |
| EF-DI-CHENC-LTE-SITE |
xilinx |
The 3GPP LTE Channel Encoder performs the 'outer' transmit functions for the Physical Downlink Shared (PDSCH)and Multicast (PMCH)and Paging (PPCH)and Control (PDCCH) and Broadcast (PBCH) channels. |
| EF-DI-CHEST-LTE-SITE |
xilinx |
LOGICORE, 3GPP LTE CHANNEL ESTIMATOR, SITE LICENSE |
| EF-DI-CHROM-RESAMP-SITE |
xilinx |
LOGICORE, CHROMA RESAMPLER, SITE LICENSE |
| EF-DI-CPRI-SITE |
xilinx |
Logicore IP Is A High-Performance, Low Cost Flexible Solution |
| EF-DI-CTC-80216E-DEC-SITE |
xilinx |
The IEEE 802.16e CTC Decoder Core performs iterative decoding of channel data that has been encoded as described in Section 8.4.9 of the IEEE Std 802.16e specification. |
| EF-DI-CTC-80216E-ENC-SITE |
xilinx |
The IEEE 802.16e CTC Encoder Core performs duo binary Turbo Encoding of channel data as described in Section 8.4.9 of the IEEE Std 802.16e specification. The coding scheme is a parallel concatenated convolutional code with an input data block of 2N bits. |
| EF-DI-DEF-PIX-CORR-SITE |
xilinx |
XLXEF-DI-DEF-PIX-CORR-SITE LOGICORE, DEF |
| EF-DI-DEINTERLACER-SITE |
xilinx |
LOGICORE, VIDEO DEINTERLACER, SITE LICENSE |
| EF-DI-DISPLAYPORT-SITE |
xilinx |
LOGICORE IP, DISPLAYPORT INTERCONNECT PROTOCOL |
| EF-DI-DPD-SITE |
xilinx |
LOGICORE, DIGITAL PRE-DISTORTION, SITE LICENSE |
| EF-DI-EAVB-EPT-SITE |
xilinx |
Ethernet Audio Video Bridging is an emerging IEEE 802.1 standard designed by Audio Video Bridging (AVB) group to provide a reliableand high quality of service and low latency solution for streaming media. |
| EF-DI-GAMMA-SITE |
xilinx |
LOGICORE, GAMMA CORRECTION, SITE LICENSE |
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